Does S20.20 ESD handling requirements still apply for Wafer fab environments?
A wafer still has active circuitry, which can be susceptible to ESD, but am not sure if that is considered as an ESD sensitive device. We can apply the cleanroom considerations for a fab to minimize the amount of contamination and dirt. But do we still need to do the E-field measurements for insulators and other ESD checks for the equipment in a fab?
Pls correct me if i am wrong, but i think that all charges are equally distributed on a wafer, making it an equipotential surface. Thus, we may not need to have the ESD checks while handling a wafer. Is this true?
Hello and welcome to the forum. You have asked a very good question. There is some thought that a wafer in most process stages are not considered an ESD sensitive device and therefore does not need the controls of ANSI/ESD S20.20 with a few exceptions.
One thing to keep in mind is there are two elements to an ESD issue, one, the device itself or some element of the process must charge and two, there needs to be a discharge. If one or both of these events can be stopped, then ESD is not an issue. ANSI/ESD S20.20 tries to prevent charge build up. Then a discharge cannot take place.
For a wafer, even with active circuits, it is often difficult to create a discharge path. There are a couple of exceptions that need to be addressed. One is wafer probe where contact is made with a device. A discharge could occur when the probe makes contact with the device.
The second consideration is where do you start an ESD control process. Most ESD control process start at a minimum when the contacts are applied to the devices. Then there are paths to the devices themselves and if charging occurs, an ESD event to a device could happen.
I hope this helps. Feel free to ask more questions.