Is it necessary to stress over +-1kv to test device based on CDM standard?

Dear all,

There’s several level that describe device CDM sensitivity, from <125 V to >1000V, and many research indicate that the lower stress voltage the more variation it could happen.

But when it comes to over CDM 1KV test, there is seldom documents or application which mention its limitation.

  1. Will the over 1KV CDM test cause the discharge to the pin which is close to the pin under test?
  2. As for low stress voltage, how much voltage is the bottom line to test as we hope the current waveform variation will not affect our testing result? lower that ±250V?
  3. For high stress voltage(over ±1000V), will the higher stress voltage increase the discharge current variation that result in incorrect CDM sensitivity level?

Kindly advise, thank you.


Hi Bruce,

I recommend that you visit the website of JEDEC (, register there and download the JEDEC publication JEP157. This publication addresses “Recommended ESD-CDM Target Levels”.


Hi Tom,

Thank you for advice! I downloaded it . JEP157 is a nice document that indicate many issue and suggestion when consider ESD sensitivity level.(BTW, I am not ESD designer, so many design technology issue in this document I could not understand totally)

A question I still wondering : Will it be needed to test device over ±1000V using CDM tester?
I concern that stress over ±1000V to test device, which might have much (current) variation, result in no discrimination.

Kindly advice, thank you.


Looking forward to receiving your feedback. Thank you.

Hi Bruce,

sorry for my late reply.

From a reliability point of view, it is not necessary to test beyond the recommended CDM targets (or to test beyond ±1000V). In fact, some years ago a paper was presented at the EOS/ESD Symposium, which showed that beyond ±1250V partial discharges may occur, which may result in a large peak current variation and even cause the peak current to decrease as the CDM stress level is further increased.

However, as ESD stress levels are concerned, there is also a “human” factor involved. Unfortunately, many people are not familiar with plasma physics and reliability testing. So, some of them used to think in linear categories, believe that passing a higher ESD target is always better than passing a lower target.


Hi TomK,

Glad to receive your detailed reply, and your feedback is important to me when conducting reliability test. Also agree with you that there are some misunderstanding regarding reliability test standard(JEDEC or JS-00X) nowadays.

Thank you!