One of our customers has given a new requirement for CDM voltage to be <50volts. The original documented requirement was to comply with ESDS 20.20 Standard which site is already complying. However, it is new requirement considering critical projects.
I would like to conduct a self-assessment and check our readiness for this requirement. So request your assistance to understand about this requirement in more details including measurement process and suggestions for compliance.
ANSI/ESD S20.20 applies to devices with sensitivities down to 200 volts CDM. It also says, “Processes that include items susceptible to lower withstand voltages may require additional control elements or adjusted limits.”
It is hard to tell you exactly what additional control elements you should add or determine any adjusted limits without an assessment of your process. Some things you may want to consider are:
Doing a process assessment per ANSI/ESD SP17.1 to determine what you need to protect the product below 50 volts CDM. This may include things like using dissipative tools and/or ionization
Possibly increase your frequency of compliance verification
Use some type of continuous monitors to ensure resistance measurements are constantly monitored
As Andy mentioned, following ANSI/ESD SP17.1 will provide the guidance needed to perform a process assessment. Since it is a lower CDM sensitivity, pay close attention to any tools, fixturing or other items that come in intimate or close contact with your device/assembly. Material selection for those will be a key component in protecting the device. Another useful document is the TR19 on High Reliability. It has several “better” practices that can apply in this situation.
The CDM withstand voltage value alone gives only limited information to estimate process related ESD risks, but knowing a bit more details, such as what pins are the sensitive ones (corner I/Os or middle pins), what peak discharge current is required to damage chip, etc. …would help to estimate safety margins. As already stated, the best method is to prevent sensitive I/Os to contact another conductive surface. When this cannot be avoided (chip assembly on board / chip testing in a fixture / chip backend processes /…) it is recommended to do extra control measures as stated in SP17.1 Annex A. Here the measured voltage and charge together would tell you if the chip has too much stored energy just prior touch, and the most detailed (and most difficult) method would be to directly measure discharge current values inside process area, and compare those to CDM test results (assuming you have CDM peak current data available).
Why is this customer requesting a CDM of less than 50 volts? Are any of the parts that sensitive? Does the customer understand that CDM is based on the parts being processed, not some arbitrary number they like? I would ask them for more information before doing anything else.
What is the actual CDM sensitivity of the part or parts of concern? If they are saying they want less than 50 volts, it makes no sense. 5 volts is less than 50 volts. Do the pats have a CDM of 5 volts? I think not. Just like 20.20 that states it is for parts with a CDM of 200 volts or more, the customer could say they want CDM protection for parts with a CDM sensitivity of greater than 50 volts.