Dear ESD expert,
Recently, ESDA had released a document " ESD Technology Roradmap" on Sep. 2024.
And I noticed that there’s a photo(Figure 12) about “CDM Die-to-Die voltage trend(below < 30 V)” in section 4.3
I wonder that how the voltage(CDM below < 30 V) be evaluated? Based on which technical paper? Or this data is sourced form the trend of CMOS “gate oxide voltage”?
Thank you. Looking forward to receiving you feedback.
Bruce,
Great question. I am not the expert in this area so I asked Brett Carn to answer this question. He said:
" The roadmap chart that is discussed in the ESDA roadmap document is a reference to the CDM ESD target level for die-to-die interfaces that exist in significant quantities in heterogeneous integration. These 2.5D/3D advanced packages incorporate die-stacking techniques that create these die-to-die interfaces. Hundreds or even tens of thousands of these die-to-die interfaces can be connected through very small size/tight-pitched micro bumps. The typical area used for standard ESD protection structures is unacceptable for these tight-pitched interfaces. Since these micro bump interfaces are only exposed to ESD risks for a small portion of package manufacturing (wafer level until the die is in the advanced package) and due to the small area needed, the CDM ESD target level can be aggressively smaller than typical CDM ESD protection needs. As shown in the roadmap it can be at 30V and is trending to even lower levels now and in the future. Therefore, these target levels are driven more by the need for small area consumption than gate oxide trends, but of course in designing any ESD protection structure, whether it be at 30V or 250V, that gate oxide failure voltage must be taken into account.
*More details on these die-to-die interfaces can be found in the Industry Council on ESD Targets White Paper 2, Part II “Die-to-Die Interfaces - A Case for Lowering Component-level CDM ESD Specifications and Requirements” (Industry Council on ESD Target Levels / Documents [esdindustrycouncil.org]), which is where this ESD targets roadmap figure originated from. In this document, you will also see more discussion on ways these lower ESD targets can be evaluated, the most promising approach being some form of contact-based CDM test method. The ESDA has standard practice documents created for both Low-Impedance Contact CDM (LICCDM, ANSI/ESD SP 5.3.3) and Capacitively-Coupled Transmission Line Pulsing (cc-TLP, ANSI/ESD 5.3.4) which are discussed in the Industry Council white paper as approaches that could be used in the future for qualification of these die-to-die interfaces."
I also received a similar reply from another colleague
“Figure 12 relates only to the internal IOs of a 2.5D/3D integrated IC. The voltage that is mentioned in the figure is the charging voltage that occurs during assembly of the 2.5D/3D IC. The voltage is evaluated by using the process assessment techniques described in SP17.1. Based on the voltage level that occurs during assembly and by knowing the size of the chiplet/die we can extract the expected CDM current. This current is used as a target for the ESD protection design.
The scaling of the voltage is not related to any gate stack thickness but to the scaling of the interconnect/bump pitch. A lower pitch results in less available area for the ESD protection at these internal IOs. A lower area results in a lower protection target that can be achieved by design. Thus the allowed charging voltage during assembly needs to be reduced by improved ESD control measures.”
Dear Mr. Nold,
Thank you so much for help!
All these info. is important for knowing more ESD topic.
I appreciate you and friend that share precise knowledge!
Bruce
I saw that ESDA released the “ESD Technology Roadmap” in September 2024, and I noticed Figure 12 in section 4.3, which shows the “CDM Die-to-Die voltage trend (below 30 V).”