Hello everyone
I am currently working on a design that requires the CDM (Charged Device Model) ESD level to be kept within 100V.
Could you please share your recommendations on what measures are most effective to achieve this? Any practical tips, design guidelines, or lessons learned would be greatly appreciated.
Thank you in advance for your help.
Best regards
Greetings of the day from India to all the members on this forum and warm welcome to OKJACK joining our community . 
I would suggest you to click and go through the exchange of information in the recent past related to measure CDM < 50 V which would give you sufficient inputs perhaps .
Many experts have shared their views .
May be once you glance at it, we all move further on this platform as it is now the changing trend on CDM effects and it is good frequent queries are appearing related to CDM issues .
Thank you .